Method and apparatus for preventing boosting system bus when charging a battery

ABSTRACT

A controllably alternating buck mode DC-DC converter conducts cycle by cycle analysis of the direction of inductor current flow to decide whether to operate in synchronous buck mode or standard buck mode for the next successive cycle. For each cycle of the PWM waveform controlling the buck mode DC-DC converter, a mode control circuit examines and latches data representative of the direction of inductor current flow relative to the chargeable battery. If the inductor current flow is positive, a decision is made to operate in synchronous buck mode for the next PWM cycle, which allows positive current to charge the battery; if the inductor current drops to zero, a decision is made to operate the converter in standard buck mode for the next PWM cycle, so as to prevent current from flowing out of the battery and boosting the system bus.

CROSS-REFERENCE TO RELATED APPLICATION

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 7,235,955. The reissue applications are reissueapplication Ser. No. 12/492,635 (the parent reissue application), issuedas U.S. Reissue Pat. No. RE42142; reissue application Ser. No.12/951,716 (a sibling, continuation reissue); and reissue applicationSer. No. 12/951,693 (the present, continuation reissue application). Allthree reissue applications are reissues of the same U.S. Pat. No.7,235,955.

This continuation reissue application Ser. No. 12/951,693, filed Nov.22, 2010 is a continuation of Ser. No. 12/492,635, filed Jun. 26, 2009,now reissued as RE42142, which is a reissue of Ser. No. 11/158,869,filed Jun. 22, 2005, now U.S. Pat. No. 7,235,955, which claims thebenefit of U.S. Provisional Application Ser. No. 60/591,203, filed onJul. 26, 2004.

The present application claims the benefit of now abandoned U.S. patentapplication Ser. No. 60/591,203, filed Jul. 26, 2004, by Eric Solie etal, entitled: “Method to Prevent Boosting the System Bus When Chargingthe Battery,” assigned to the assignee of the present application andthe disclosure of which is incorporated herein.

FIELD OF THE INVENTION

The present invention relates in general to power supply systems andsubsystems thereof, and is particularly directed to a method andapparatus for controllably switching the operation of a buck mode DC-DCconverter between synchronous buck mode and standard buck mode in amanner that is effective to prevent boosting the voltage of the systembus in the course of the buck mode converter charging a battery.

BACKGROUND OF THE INVENTION

FIG. 1 is a reduced complexity circuit diagram of a typical synchronousbuck mode DC-DC converter architecture for charging a battery by way ofa voltage that is supplied to the charger circuitry and to downstreampowered circuitry from an AC-DC adapter. As shown therein, a poweredsystem bus 10 is coupled to a system power source such as an AC-DCadapter, which is operative to supply a prescribed DC voltage, such as avoltage value on the order of sixteen to nineteen volts DC, that is tobe available for powering one or more system bus loads 12, which areconnected between the powered bus 10 and a reference voltage bus 14,such as a zero volts or ground bus. In addition to supplying a DCvoltage to system bus components, the system bus is employed to chargean auxiliary power storage device, such as a battery 16.

For this purpose, an upper controlled switch or MOSFET 21 and a lowercontrolled switch or MOSFET 23 have their source-drain paths coupled inseries between the system bus 10 and the reference voltage bus 14. Thegates of these two MOSFETs are adapted to be driven by respective(complementary) pulse width modulation (PWM) signals supplied thereto bya PWM controller. The common or phase node 25 between the upper MOSFETor UFET 21 and the lower MOSFET or LFET 23 is coupled by way of aninductor 27 to an output node 29 to which the battery 16, referenced tothe ground bus 14, is coupled. In addition, a capacitor 33 is coupledbetween output node 29 and the ground reference bus 14.

Now although the use of a synchronous buck mode DC-DC converterarchitecture provides a relatively efficient mechanism for charging thebattery, its operation can lead to the delivery of a negative or reversecurrent from the battery charger onto the system supply bus 10, therebyincreasing the system bus voltage to unsafe levels that may damagedownstream system components. Such a flow of negative current can resultfrom a number of events, such as, but not limited to, soft starting thecharger, inserting the battery, and removing the adapter voltage. Inthese events, the charger is operating open loop with a duty cycle thatis lower than the closed loop duty cycle. It is possible to boost thesystem bus, if negative inductor current is flowing, namely, away fromthe battery opposite the direction of the arrow A, which shows thedirection of positive inductor current flow into the battery, and whenthe system bus load is low (i.e., the powered system, such as a laptopcomputer is off and the battery is being charged). Current boosting intothe system bus cannot go into the AC-DC adapter (as it is not designedto sink current), or be used by the load (which is turned off), so thatthe system bus voltage rises.

The mechanism through which negative current makes its way to the systembus is as follows. When the UFET 21 is turned off and the LFET 23 isturned on, the current in inductor 27 will decrease to zero and thenbecome negative, and current will begin to flow from the battery throughthe inductor 27 in the negative direction, and down through the LFET tothe return bus or ground. This is the current loop through which currentwill flow when the LFET 23 is on. When the LFET is turned off, thecurrent that has built up in the inductor 27 cannot go through the LFET,and instead flows through the body diode of the UFET 21 to the supplybus 10, thereby undesirably boosting the supply bus voltage, typicallyby a value on the order of several or more volts—high enough to damageloads connected to the system bus.

To address this problem, designers of synchronous buck mode DC-DCconverters have commonly employed a mechanism, known as diode emulation,which causes the LFET to behave as though it were a diode. In this diodeemulation mode, the direction of current flow through the LFET ismonitored. As long as current is flowing in the positive direction (fromthe source to the drain) the LFET 23 is allowed to be turned on.However, if the current reaches zero or goes negative, then the lowerFET is turned off. This effectively makes the lower FET emulate a diode,in that the LFET allows positive current to flow through it (upwardlyfrom the source to the drain and out through the inductor in thepositive direction), but blocks current in the opposite or negativedirection, in that no current is allowed to flow through the LFET in thedrain-to-source direction, once the current reaches a zero value.

A reduced complexity schematic of a conventional circuit forimplementing this diode-emulation control function is showndiagrammatically in FIG. 2, as comprising a phase comparator 40, havingits positive or non-inverting (+) input 41 coupled to the drain and itsnegative or inverting (−) input 42 coupled to the source of LFET 23. Theoutput of the phase comparator 40 is coupled to one input of a NOR gate45, a second input of which is coupled to receive the PWM signal. Theoutput of NOR gate 45 is coupled through a driver 46 to the gate inputof LFET 23. Similarly, the PWM signal is coupled through a driver 47 tothe gate input of UFET 21, and further to a delay circuit 50, the outputof which is coupled to the disable input of phase comparator 40. Delaycircuit 50 is used to disable or ‘blank’ the operation of phasecomparator 40 for a prescribed time delay (e.g., on the order of 200 ns)subsequent to the rising edge of the PWM signal, to allow ringing at thephase node 25 associated with the inductance of inductor 27 and theparasitic capacitance of the phase node 25 to subside sufficiently toallow an accurate measurement of current flow.

The operation of the circuit of FIG. 2 may be understood with referenceto the set of waveforms shown in FIG. 3. When the PWM waveform shown at300, transitions from high to low at time 301, the voltage at the phasenode 25, which had previously been at Vin due to the conduction of UFET21, will undergo negative ringing below zero volts as shown by theringing portion 311 of phase node voltage waveform 310. Because theringing associated with the PWM transition constitutes noise, theoperation of the phase comparator 40 is blanked by the delay circuit 50for a period of time that allows the ringing to subside. At the end ofthe ringing interval shown at 312, the phase node voltage is negativeand begins a gradual transition towards zero volts as the inductorcurrent gradually transitions towards zero as shown at 313. At thispoint, the inductor current can be validly measured.

A voltage representative of the inductor current is produced by theon-resistance of the LFET 23 and value of the negative inductor currentflowing from the drain to the source of LFET 23. Because the source ofLFET 23 is connected to ground, then when the current ispositive—flowing from source to drain—the voltage at the phase node isactually below ground, as shown at 313, referenced above. Once thevoltage at the phase node has increased to zero volts, at time 314, theoutput of the phase comparator 40 changes state and, via NOR gate 45,turns off the LFET 23, so that the LFET will act as a diode for negativeinductor current.

The waveforms of FIG. 4 illustrate a fundamental problem with themechanism employed in the circuit of FIG. 3. If diode emulation were notemployed, then the PWM signal for controlling the turn on/off of theLFET 23 would be the complement of the PWM signal employed for the UFET21. However, since diode emulation is controlled by the presence of thedelay circuit 50, the NOR gate 45, and the phase comparator 40, the LFET23 has a shorter on time than the inverse of PWM waveform applied to thegate of UFET 21. The top waveform 400 of FIG. 4 corresponds to the PWMsignal that is applied to the gate UG of the UFET 21, while the bottomwaveform 420 corresponds to the PWM signal that is applied to the gateLG of the LFET 23. The intermediate waveform 410 in FIG. 4 representsthe variation in the inductor current through inductor 27.

As shown in FIG. 4, in response to the rising edge 401 in the PWMwaveform 400 applied to the gate UG of the UFET 21, inductor currentbegins a positive ramp at 411, until the high-to-low transition 402 inthe PWM waveform 400. In response to this transition, the UFET 21 isturned off, and the inductor current begins ramping down towards 0 amps,as shown at 412. In addition, when the PWM waveform applied to gate ofthe UFET 21 goes low, the waveform 420 applied to the gate of the LFET23 goes high at 421, thereby turning on the LFET 23. During the intervalbetween the high-to-low transition 402 in the PWM waveform applied togate UG of the UFET 21 and the time 413 at which the inductor currentreaches zero, positive inductor current is being supplied by the LFET23, which has been turned on by the low-to-high 421 transition in the LGPWM signal 420.

The positive inductor current being supplied by LFET 23 flows from itssource, which is at ground potential, to its drain, which is at a phasenode voltage negative with respect to ground. When the inductor currentreaches zero amps (0 A) at time 413, one would like to turn off the LFET23. However, due to the use of the delay/blanking interval 414, theinductor current is not being monitored, so that no turn off signal isapplied to the gate of the LFET 23. Instead, the inductor currentcontinues to decrease well below zero amps, as shown at 415. Finally, atthe end of the blanking interval, the output of the phase comparator 40,which has detected that Vd>Vs, is allowed to indicate that negativeinductor current has been detected, and the LFET 23 is turned off. Thisis shown in FIG. 4 by the high-to-low transition 422 of the gate controlwaveform LG 420 to the gate input of the LFET 23.

When the LFET 23 turns off, the phase node 25 will go from zero volts toa diode drop above Vin, so that the body diode of UFET 21 is conducting.With both UFET 21 and LFET 23 now turned off, the negative polarityinductor current begins to ramp up towards zero amps, as shown at 416.During this transition, the negative inductor current is flowing throughthe body diode of the UFET 21. Eventually, at 417, the ramping upnegative current reaches zero amps and the cycle described aboverepeats.

An examination of the inductor current waveform 410 reveals that theaverage inductor current is negative, as shown by broken lines 418. Thismeans that an average negative current is being supplied by the batteryinto the system bus—placing the system bus 10 at an undesirably highvoltage value. It will be readily appreciated, therefore, that withinthe blanking interval 414 a fairly large negative inductor current isrealized. If the battery voltage is relatively high and the value L ofthe inductor 27 is relatively low, then di/dt is relatively large;namely, the inductor current reaches a relatively large negative valuewithin a relatively small window of time. One way to mitigate againstthis effect is to reduce the blanking interval. However, doing socreates the risk that the phase comparator will trigger on a ringingedge rather than on a true zero-crossing ramp, as described above withreference to FIG. 3. As pointed out above, the ringing is due to theparasitic capacitance of the phase node and the value of the inductance.The blanking interval must be kept sufficiently wide to allow theringing voltage at the phase node to subside. However, doing so meansthat there will be a fairly substantial average negative inductorcurrent presented to the system bus, which is the problem to be solved.

SUMMARY OF THE PRESENT INVENTION

Pursuant to the present invention, shortcomings of prior art synchronousbuck mode-based battery chargers, including those described above withreference to FIGS. 1-4, are successfully remedied by a controllablyalternating buck mode DC-DC converter, that is selectively switchedbetween synchronous buck mode and standard buck mode, in a manner thatis effective to prevent boosting the voltage of the system bus in thecourse of the buck mode converter charging a battery. For this purpose,the invention comprises a memory augmentation to the prior art circuitof FIG. 2, described above, that examines and latches a data bitrepresentative of the direction of inductor current flow relative to thechargeable battery for each cycle of the PWM waveform that controls theoperation of the buck mode DC-DC converter. If the direction of outputinductor current flow is positive (into the battery) at the rising edgeof PWM, the converter is operated in synchronous buck mode for the nextPWM cycle, on the other hand, if the direction of current flow at therising edge of PWM is tending to be negative (out of the battery), inparticular if the inductor current drops to zero, the converter isoperated in standard buck mode for the next PWM cycle, so as to preventcurrent from flowing out of the battery and boosting the system bus.

To this end, the memory augmentation of the buck mode DC-DC convertercircuit of FIG. 2 involves the incorporation of a D-type flip-flophaving its D input coupled to the output of the phase comparator, itsclock input CK coupled to receive the PWM waveform, and its Q outputcoupled as an additional input to the NOR gate. The state of the Qoutput of the flip-flop determines whether the converter is to operatein synchronous buck mode or standard buck mode. When operating instandard buck mode, the Q output of the flip-flop is latched high, whichkeeps the LFET turned off, so that the converter is effectivelyconfigured as a standard buck mode converter, having a PWM controlledUFET and a body diode of the LFET. Since, in this mode, the LFEToperates as a diode, inductor current is prevented from going negative,as the body diode of the LFET will effectively block negative currentflow. Therefore, where inductor current shows a tendency to or ‘starts’to go negative (i.e. drops to zero) within the blanking interval, theLFET's body diode will block the current the moment the inductor currentreaches zero amps.

The flip-flop monitors the output of phase comparator on the rising edgeof the PWM waveform, which serves as the clock (CK) input to theflip-flop. The flip-flop latches the state of the phase comparator anduses this stored information for the next PWM cycle. If, on the risingedge of the PWM waveform, the phase comparator indicates that theinductor current is positive (into the battery), the LFET is allowed toturn on. Namely, where the inductor current is positive, the drain ofthe LFET will be below ground; therefore, the output of the phasecomparator goes low (‘0’), which is clocked into the flip-flop, so thatthe Q output of flip-flop goes low. As a consequence, two of the threeinputs to the NOR gate are low, so that the NOR gate will be effectivelycontrolled by its remaining input, which is the PWM waveform. Therefore,in response to a low-to-high transition in the PWM waveform, the outputof the NOR gate goes low, so that the LFET will be turned off. Until thenext rising edge of the PWM waveform, the Q output of flip-flop willremain low for an entire PWM period. Since the Q output of the flip-flopis low, the next time the PWM waveform goes low, all inputs to the NORgate will be low, so that the output of the NOR gate will be high (‘1’),thereby turning on the LFET, so that the converter operates insynchronous buck mode.

If, on the other hand, on the rising edge of the PWM waveform, theinductor current has dropped to zero, then the drain of the LFET will bepositive (above ground). As a result, the output of the phase comparatorwill be high. This high (‘1’) state is clocked into the flip-flop on therising edge of the PWM waveform, so that the Q output of the flip-flopis high (‘1’). Since a high on any input of the NOR gate will force itsoutput low, the low output of the NOR gate will now force the LFET to beturned off for the entire period. In this condition, the LFET behaves asa diode, so that the converter operates as a standard buck modeconverter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a reduced complexity circuit diagram of a typical synchronousbuck mode DC-DC converter for charging a battery by way of a voltagethat is supplied to the charger circuitry and to downstream poweredcircuitry from an AC-DC adapter;

FIG. 2 is a reduced complexity schematic of a conventional circuit forimplementing a diode-emulation control function in a synchronous buckmode DC-DC converter of the type shown in FIG. 1;

FIGS. 3 and 4 are respective sets of waveforms associated with theoperation of the circuit of FIG. 2;

FIG. 5 shows a memory augmentation of the buck mode DC-DC convertercircuit of FIG. 2 in accordance with an embodiment of the presentinvention, that controllably switches the converter between synchronousbuck mode and standard buck mode operation, in a manner that iseffective to prevent boosting the voltage of the system bus;

FIG. 6 is a set of waveforms showing a transition in the operation ofthe converter of FIG. 5 from synchronous buck mode to standard buckmode;

FIG. 7 is a set of waveforms showing a transition in the operation ofthe converter of FIG. 5 from standard buck mode to synchronous buckmode; and

FIG. 8 is an inductor current waveform associated with the operation ofFIG. 5.

DETAILED DESCRIPTION

Attention is now directed to FIG. 5, which shows a modification of thebuck mode DC-DC converter circuit of FIG. 2 in accordance with anembodiment of the present invention, to include a memory element that isused to selectively latch the output of the phase detector and therebycontrol the switching of the operation of the converter betweensynchronous buck mode and standard buck mode operation, in a manner thatis effective to prevent boosting the voltage of the system bus. Inparticular, FIG. 5 shows the addition of a D-type flip-flop 60 havingits D input coupled to the output of the phase comparator 40, its clockinput CK coupled to receive the PWM waveform, and its Q output coupledas an additional input to NOR gate 45. As will be described below, thestate of the Q output of flip-flop 60 determines whether the converteris to operate in synchronous buck mode or standard buck mode.

When operating in standard buck mode, LFET 23 is held off, so that onlyits body diode participates in the operation of the circuit. Namely,when the Q output of flip-flop 60 is such as to hold LFET 23 turned off,the converter is effectively configured as a standard buck modeconverter having a PWM controlled UFET 21 and a diode LFET 23. Since, inthis mode, the LFET operates as a diode, inductor current is preventedfrom going negative, since the body diode of the LFET will effectivelyblock negative current flow. Therefore, even if, as in waveform diagramof FIG. 4, inductor current shows a tendency to or ‘starts’ to gonegative (i.e. drops to zero) within the blanking interval, the LFET'sbody diode will block the current the moment the inductor currentreaches zero amps. It may be noted that if both the UFET and the LFETare turned off, and the inductor current is positive, it flows throughthe body diode of the UFET.

The function of the flip-flop 60 is to monitor the output of phasecomparator 40 on the rising edge of the PWM waveform, which serves asthe clock (CK) input to the flip-flop. The flip-flop stores or remembersthe state of the phase comparator and uses this stored information forthe next PWM cycle. The phase comparator is used to indicate in whatdirection inductor current is flowing. Namely, if, on the rising edge ofthe PWM waveform, phase comparator 40 indicates that the inductorcurrent is positive (in the direction of arrow A into the battery), LFET23 is allowed to turn on.

As pointed out above, if the inductor current is positive, the drain ofLFET 23 is below ground; therefore, in response to a negative polarityvoltage applied to the non-inverting (+) input 41, the output of phasecomparator 40 goes low (‘0’). This low or ‘0’, in turn, is clocked intothe D input of flip-flop 60, so that the Q output of flip-flop 60 goeslow. As a consequence, the bottom two inputs 45-1 and 45-2 to NOR gate45 are low, so that the controlling input to NOR gate 45 will be the PWMwaveform, which is applied to input 45-3. By virtue of its NOR function,gate 45 will produce a ‘0’ at its output if any of its inputs is a highor ‘1’, and will produce a ‘1’ at its output, only if all of its inputsare low (‘0’s).

Thus, in response to a low-to-high transition in the PWM waveform, whichis applied to input 45-3 of NOR gate 45, the output of NOR gate 45 willbe low, so that the LFET 23 will be turned off. Until the next risingedge of the PWM waveform, the Q output of flip-flop 60 will remain lowfor an entire PWM period. Since the Q output of flip-flop 60 is low, thenext time PWM goes low, all of the inputs to the NOR gate 60 will below, so that the output of the NOR gate will be high (‘1’), therebyturning on LFET 23, so that the converter operates in synchronous buckmode.

If, on the other hand, on the rising edge of the PWM waveform, theinductor current has dropped to zero, then the drain of LFET 23 will bepositive (above ground). As a result, the output of the phase comparator40 will be high. This high (‘1’) state is clocked into the D input offlip-flop 60 on the rising edge of the PWM waveform, so that the Qoutput of flip-flop 60 is high (‘1’). As pointed out above, a high onany input of NOR gate 45 will force its output low. Therefore, in thisstate, the output of NOR gate 45 will force LFET 23 to be turned off forthe entire period. In this condition, LFET 23 behaves as a diode, sothat the converter operates as a standard buck mode converter.

The manner in which the memory function of flip-flop 60 is used toselectively switch the converter between standard buck mode andsynchronous buck node may be readily understood with reference to FIGS.6 and 7, wherein FIG. 6 is a set of waveforms showing a transition inthe operation of the converter from synchronous buck mode to standardbuck mode (going from a high output current to a low output current),while FIG. 7 is a set of waveforms showing a transition in the operationof the converter from standard buck mode to synchronous buck mode (goingfrom a low output current to a high output current).

Referring now to FIG. 6, an upper PWM waveform 600 is shown ascomprising a sequence of PWM pulses 601, 602, 603, 604, 605, . . . ,which are applied to the gate of UFET 21. As will be described over thecourse of this sequence of PWM pulses, the converter of FIG. 5 isoperative to transition from synchronous buck mode to standard buckmode. With the converter initially operating in synchronous buck mode,then at the rising edge 601-1 of the first PWM pulse 601 of PWM waveform600, UFET 21 is turned on, and at the falling edge 601-2 of PWM pulse601, which corresponds to the rising edge 611-1 of pulse 611 of thedrive waveform 610 (LG) to the gate of LFET 23, LFET 23 is turned on.Namely, being in synchronous buck mode, the PWM drive to LFET 23 iscomplementary to the PWM drive to UFET 21. As is further shown in theinductor current waveform 620, during this time the inductor current isincrementally ramping down; there is an increasing ramp 621 in theinductor current during the high state of the PWM pulse 601, and adecreasing ramp 622 in the inductor current during the high state of theLG pulse 611.

As can be seen from an examination of the left hand side of the inductorcurrent waveform 620, during synchronous buck mode, the inductor currenthas a positive value. Waveform 630, which represents the voltage at thephase node 25, shows the phase node voltage transitioning to Vin at 631,when the UFET 21 is turned on by the PWM pulse 601 in the waveform 600,and then dropping at 632 to a prescribed voltage value below ground(e.g., on the order of −50 mV), when the UFET 21 is turned off and LFET23 is turned on. Thereafter, as shown at 633, the phase node voltagegradually ramps up towards ground (zero volts) as the inductor current622 decays.

The bottom waveform 640 shows the state of the Q output of the Dflip-flop 60 during this time. As described above, during synchronousbuck mode, the low output of phase comparator 40 is clocked into Dflip-flop 60 and its Q output remains low for a complete cycle. Sincethe Q output of flip-flop 60 is low, the next time PWM goes low, all ofthe inputs to the NOR gate 60 will be low, so that the output of the NORgate will be high (‘1’), thereby turning on LFET 23, and the converteroperates in synchronous buck mode.

Referring again to the upper PWM waveform 600, at the rising edge 602-1of the second PWM pulse 602, UFET 21 is again turned on, and at thefalling edge 602-2 of PWM pulse 602, which corresponds to the risingedge 612-1 of pulse 612 of the drive waveform 610 (LG) to the gate ofLFET 23, UFET 21 is turned off, and LFET 23 is turned on. Namely, stillbeing in synchronous buck mode, the PWM drive to LFET 23 iscomplementary to the PWM drive to UFET 21.

In the inductor current waveform 620, the inductor current continues toincrementally ramp down toward zero amps; there is another increasingramp 623 in inductor current during the high state of the PWM pulse 602,and a decreasing ramp 624 in inductor current during the high state ofthe LG pulse 612. During the high state of the PWM pulse 602, the phasenode voltage is again at the input voltage Vin, as shown at 634, as UFET21 is turned on by pulse 602 in the PWM waveform 600, and then drops at635 to a voltage value below ground (e.g., on the order of −25 mV), whenthe UFET 21 is turned off and LFET 23 is turned on. As shown at 636, thephase node voltage gradually ramps up towards ground (zero volts) as theinductor current 624 decays.

During the high state of the LG pulse 612, the inductor current has adecreasing ramp 624. However, unlike the previous cycle, rather thanbeing at a positive current value when the next PWM pulse is asserted,ramp 624 reaches zero at time 625 prior to the next PWM pulse 603. Asdescribed above, in accordance with the operation of the converter ofFIG. 5, when the inductor current drops to zero amps, the output of thephase comparator 40 goes high, so that the output of NOR gate 45 goeslow, and LFET 23 is turned off, as shown at high-to-low transition edge612-2 of waveform 610. With LFET 23 being turned off, the phase nodevoltage rings from zero volts up to Vout (Vo), as shown at 637, and thenstays at Vo, as shown at 638 in waveform 630.

At the rising edge 603-1 of the next PWM pulse 603, the high (‘1’)output of phase comparator 40 will be clocked into flip-flop 60, so thatits Q output goes high, as shown at 641 of waveform 640, whichrepresents the Q state of flip-flop 60, and holds LFET 23 off. UFET 21is turned on by the rising edge 603-1 of PWM pulse 603, so that thephase node voltage rises to Vin, as shown at 639; in addition, theinductor current begins ramping up, as shown by increasing ramp portion626 of inductor current waveform 620. Next, on the falling edge 603-2 ofPWM pulse 603, since the Q output of flip-flop 60 is high, LFET 23 isprevented from turning on. As a result, the LG waveform 610 remains low,so that when UFET 21 turns off at 603-2, positive inductor current willflow through the LFET 23 body diode and pull the drain of the LFET onediode drop below ground. The phase node voltage therefore drops to avalue on the order of −700 mV, as shown at 650 in the phase node voltagewaveform 630, as current is flowing from the source to the drain of LFET23.

In response to the falling edge 603-2 of PWM pulse 603, UFET 21 isturned off and inductor current begins to ramp down toward zero, asshown at 627 in the inductor current waveform 620. When the inductorcurrent reaches zero at 628, the phase node voltage will rise, as shownas 651 in phase node voltage waveform 630. When the phase node voltagerises above zero volts, the body diode of LFET 23 will block current,therefore the inductor current will stop decreasing and will stay atzero amps. The phase node voltage will then ring up to the outputvoltage level as shown at 652 of phase node voltage waveform 630.

In standard buck mode operation, when UFET 21 is turned on (by a risingedge in the PWM waveform), inductor current is positive and rises; then,when the UFET 21 is turned off (as the PWM waveform transitions low),current will flow through the body diode of the LFET 23 until theinductor current reaches zero, at which time the phase node voltage willrise to the value of Vout or the battery voltage. There is no currentflowing through the inductor, therefore no voltage drop across theinductor, so that the phase node voltage equals Vout.

On the next rising edge of the PWM waveform, namely, the rising edge604-1 of PWM pulse 604, with the phase node voltage being very positive(Vout), the output of phase comparator 40 is high, which again getsclocked into the flip-flop 60 maintaining its Q output high, and forcingthe output of NOR gate 45 to remain low (‘0’), so that the LFET 23 ismaintained off, thus sustaining standard buck mode operation at lowcurrent for the next cycle of the PWM waveform. This operation isrepeated for each PWM cycle, so that the mode in which the converter isto operate is determined on a cycle by cycle basis on the rising edge ofeach PWM pulse.

From the foregoing it will be appreciated that the state of the Q outputof flip-flop 60 defines the mode of operation of the converter. If the Qoutput is low, the converter operates in synchronous buck mode allowingthe LFET 23 to be turned on; if the Q output is high, the converteroperates in standard buck mode, wherein LFET 23 is maintained off.

Attention is now directed to FIG. 7, which is a set of waveforms showinga transition in the operation of the converter from standard buck modeto synchronous buck mode (going from a low output current to a highoutput current). Again, as in the case of FIG. 6, FIG. 7 depicts anupper PWM waveform 700, containing a sequence of PWM pulses 701, 702,703, 704, 705, . . . , which are applied to the gate of UFET 21. As willbe described, over the course of this sequence of PWM pulses, theconverter of FIG. 5 is operative to transition from standard buck modeto synchronous buck mode.

With the converter initially operating in standard buck mode, then, onthe rising edges of the first two PWM pulse 701 and 702 of PWM waveform700 when UFET 21 is turned on, the phase node voltage is at Vout, whichmeans that the output of phase comparator 40 will be high (‘1’). Thishigh output of the phase comparator is clocked into flip-flop 60, sothat its Q output is high, forcing the output of NOR gate 45 to be low,and thereby maintaining the gate drive LG to LFET 23 low so, as shown atthe low portion 711 of waveform 710, and keeping LFET 23 turned off, asdescribed above, in connection with the standard buck mode operation ofFIG. 6.

During the on times of the PWM pulses, UFET 21 is turned on, so thatinductor current ramps up from zero amps as shown at 721 and 722 ininductor current waveform 720. When UFET 21 is turned off in response tothe high-to-low transitions of the pulses 701 and 702 in the PWMwaveform, the inductor current gradually ramps down through the bodydiode toward zero, as shown at 723 and 724. This pulls the phase node abody diode below ground (e.g., on the order of −700 mV) as shown at 731and 732 in waveform 730. Because of the body diode, the slope of thedecrease in inductor current is proportional to the sum of the outputvoltage Vout and the body diode voltage drop Vbe.

At rising edge 703-1 of PWM pulse 703, the positive inductor current hasnot yet decreased to zero amps, as shown at 725, and the phase node 25is still a body diode voltage drop (−700 mV) less than zero volts. Sincethis voltage is coupled to the non-inverting (+) input 41 of the phasecomparator 40, the output of the phase comparator goes low. This lowoutput is applied to the D input of flip-flop 60, and is clocked intothe flip-flop 60 on the rising edge 703-1 of PWM pulse 703. The Q outputof flip-flop 60 is now low, as shown at transition 741 in the flip-flopQ waveform 740, so that inputs 45-2 and 45-1 to NOR gate 45 are bothlow.

This represents a transition from standard buck mode to synchronous buckmode. NOR gate input 45-3 is high, due to the high state of PWM pulse703. The falling edge 703-2 of PWM pulse 703 causes all inputs to theNOR gate 45 to be low, so that the output of NOR gate 45 goes high,whereby the control waveform 710 applied to the gate of LFET 23 goeshigh, as shown at 712 in waveform 710, turning on LFET 23. The operationof the converter now proceeds as described above with reference to FIG.6 for the synchronous mode of operation, with the gate drive to the LFET23 being the complement of the gate drive to the UFET 21, which is thePWM waveform. This causes the inductor current to gradually ramp up, asshown at inductor current ramp segments 726-727-728-729.

As shown in the phase node voltage waveform 730, the phase node voltageramps up slowly, but is still negative (e.g., on the order of −10 mV),due to the drop across the on-resistance of the LFET 23. Since theinductor current is positive, the phase node voltage is slightlynegative; with the phase node voltage being negative, a low isrepetitively clocked out from the phase comparator 45 into the D inputof flip-flop 60, so that its Q output is low (‘0’), whereby inputs 45-2and 45-1 to NOR gate 45 remain low. This allows the change in state ofthe PWM input 45-3 to repetitively turn on LFET 23 during the low stateof the PWM waveform.

The point at which a transition occurs between the two operational modes(synchronous buck mode and standard buck mode) of the converter of FIG.5, may be readily understood by reference to the inductor currentwaveform of FIG. 8. The transition between the two modes will occur at acontinuous conduction mode—discontinuous conduction mode boundary,namely just at a point wherein the inductor current reaches zero ampsand ramps up on the next rising edge of the PWM waveform. In particular,FIG. 8 shows a variation of inductor current with time. For a positivecurrent ramp, the slope (di/dt) is proportional to the differencebetween the value of system bus voltage (Vi) and battery voltage (Vout).As shown in FIG. 8, inductor current rises from zero amps to a peakcurrent over a time duration dT. After the peak time dT, the inductorcurrent ramps down to zero at time T. The slope (di/dt) of the fallingramp is equal to −Vout/L. By setting the change in current for a risingramp to a change in current for a falling ramp equal to each other, theaverage value of inductor current Io can be determined. Using the basicinductor voltage/current relationship:V=Ldi/dt,

then,(Vi−Vout)/L=2Io/dT=2Io/(T(Vo/Vi)).Solving for Io,Io=(1−(Vout/Vi))Vo(T/2L).

It should be noted that in the course of transitioning from standardbuck mode to synchronous buck mode, it is not possible to have negativeinductor current. As noted above, the present invention prevents theflow of negative inductor current by discriminating between positiveinductor current and ‘tending’ toward negative or ‘zero’ inductorcurrent. If positive inductor current is flowing, the phase node voltageis one body diode drop (Vbe) below ground (e.g., −700 mV); for zeroinductor current, the phase node voltage is equal to Vout.

When the converter is operating in standard buck mode, the slope of thefalling ramp of the inductor current, namely di/dt, is equal to−(Vout+Vbe)/L, where L is the inductance of inductor 27, since LFET 23has a body diode drop across it, as described above. When the converteris operating in synchronous buck mode, LFET 23 is no longer a diode, butis essentially shorted out, so that the Vbe term goes to zero. Thischanges the slope di/dt of the falling ramp to −Vout/L.

As will be appreciated from the foregoing description, drawbacks of aconventional synchronous buck mode-based battery charger of the typedescribed above with reference to FIGS. 1-4, are effectively obviated bythe controllably alternating buck mode DC-DC converter of the presentinvention, which uses a cycle by cycle analysis of the direction ofinductor current flow to decide whether the converter is to operate insynchronous buck mode or standard buck mode for the next successivecycle. For each cycle of the PWM waveform, that controls the operationof the buck mode DC-DC converter, the invention examines and latches adata bit representative of the direction of inductor current flowrelative to the chargeable battery. If the direction of output inductorcurrent flow is positive, a decision is made that the converter is tooperate in synchronous buck mode for the next PWM cycle, so as to allowpositive current to charge the battery; on the other hand, if theinductor current drops to zero, a decision is made to operate theconverter in standard buck mode for the next PWM cycle, so as to preventcurrent from flowing out of the battery and boosting the system bus.

It may be noted that an alternative methodology of the present inventioninvolves an examination of more than one cycle of the waveform beforeswitching the operational mode. As a non-limiting example, a decisioncould be made to switch modes after having three consecutive readingseach of which indicates that a mode switch should be effected.

While we have shown and described an embodiment in accordance with thepresent invention, it is to be understood that the same is not limitedthereto but is susceptible to numerous changes and modifications asknown to a person skilled in the art. We therefore do not wish to belimited to the details shown and described herein, but intend to coverall such changes and modifications as are obvious to one of ordinaryskill in the art.

1. A controllably alternating buck mode DC-DC converter comprising: anupper switching stage and a lower switching stage having controlledcurrent flow paths therethrough coupled between an input voltageterminal adapted to receive an input voltage, and a reference voltageterminal adapted to receive a reference voltage, a common node betweensaid upper switching stage and said lower switching stage being coupledthrough an output inductor to an output port for charging a battery,said upper switching stage having an upper control terminal to which afirst pulse width modulation (PWM) waveform is applied for controllingthe conduction and non-conduction of said upper switching stage, andwherein said lower switching stage has a lower control terminal to whicha second PWM waveform, referenced to said first PWM waveform, isselectively applied for controlling the conduction and non-conduction ofsaid lower switching stage; and a lower switching stage controller,which is operative, in response to a positive inductor current flow fromsaid common node to said output port at the end of one or more cyclesincluding a respective ith cycle of said first PWM waveform, to allowsaid second PWM waveform to be applied to said lower control terminal ofsaid lower switching stage during the (i+1)th cycle of said first PWMwaveform, and thereby cause said buck mode DC-DC converter to operate insynchronous buck mode for the (i+1)th cycle of said first PWM waveform,and in response to inductor current dropping to zero during said one ormore cycles including said respective ith cycle of said first PWMwaveform, to cause diode emulation of said lower switching stage duringthe (i+1)th cycle of said first PWM waveform, and thereby cause saidbuck mode DC-DC converter to operate in standard buck mode for the(i+1)th cycle of said first PWM waveform.
 2. The DC-DC converteraccording to claim 1, wherein said lower switching stage controller isoperative to store information representative of the direction ofinductor current flow for said ith cycle of said first PWM waveform, andto selectively cause said buck mode DC-DC converter to operate in eithersynchronous buck mode or standard buck mode for the (i+1)th cycle ofsaid first PWM waveform, based upon said information.
 3. The DC-DCconverter according to claim 2, wherein said lower switching stagecontroller comprises: a phase detector having inputs thereof coupledacross the current flow path through said second switching stage, and anoutput coupled to a logic circuit, a flip-flop having an input coupledto said output of said phase detector, a clock input coupled to receivesaid first PWM waveform, and an output coupled to said logic circuit,said logic circuit being coupled to receive said first PWM waveform andhaving an output coupled to said lower control terminal of said lowerswitching stage.
 4. The DC-DC converter according to claim 3, whereinsaid lower switching stage controller further comprises a blankingcircuit which is operative to controllably disable said phase detectorfor a prescribed period of time following the termination of said firstPWM waveform.
 5. The DC-DC converter according to claim 1, wherein, inresponse to a positive inductor current flow from said common node tosaid output port at the end of said one or more cycles including saidrespective ith cycle of said first PWM waveform, said lower switchingstage controller is operative to generate said second PWM waveform asthe complement of said first PWM waveform, for application to said lowercontrol terminal of said lower switching stage during the (i+1)th cycleof said first PWM waveform, and thereby cause said buck mode DC-DCconverter to operate in synchronous buck mode for the (i+1)th cycle ofsaid first PWM waveform.
 6. The DC-DC converter according to claim 1,wherein, in response to a zero inductor current during said one or morecycles including said respective ith cycle of said first PWM waveform,said lower switching stage controller is operative to prevent saidsecond PWM waveform from being applied to said lower control terminal ofsaid lower switching stage during the (i+l)th cycle of said first PWMwaveform, and thereby cause said buck mode DC-DC converter to operate instandard buck mode for the (i+1)th cycle of said first PWM waveform. 7.The DC-DC converter according to claim 1, wherein said upper switchingstage comprises an upper MOSFET and said lower switching stage comprisesa lower MOSFET, and wherein said lower switching stage controller isoperative, in response to a positive inductor current flow from saidcommon node to said output port at the end of said one or more cyclesincluding said respective ith cycle of said first PWM waveform, to allowsaid second PWM waveform to be applied to a gate terminal of said lowerMOSFET stage during the (i+1)th cycle of said first PWM waveform, andthereby turn on said lower MOSFET and cause said buck mode DC-DCconverter to operate in synchronous buck mode for the (i+1)th cycle ofsaid first PWM waveform and, in response to inductor current dropping tozero during said one or more cycles including said respective ith cycleof said first PWM waveform, to turn off said lower MOSFET during the(i+1)th cycle of said first PWM waveform, and thereby cause said buckmode DC-DC converter to operate in standard buck mode for the (i+1)thcycle of said first PWM waveform.
 8. A method of operating a buck modeDC-DC converter comprised of an upper switching stage and a lowerswitching stage having controlled current flow paths therethroughcoupled between an input voltage terminal adapted to receive an inputvoltage, and a reference voltage terminal adapted to receive a referencevoltage, a common node between said upper switching stage and said lowerswitching stage being coupled through an output inductor to an outputport for charging a battery, said upper switching stage having an uppercontrol terminal to which a first pulse width modulation (PWM) waveformis applied for controlling the conduction and non-conduction of saidupper switching stage, and wherein said lower switching stage has alower control terminal to which a second PWM waveform, referenced tosaid first PWM waveform, is selectively applied for controlling theconduction and non-conduction of said lower switching stage, said methodcomprising the steps of: (a) in response to a positive inductor currentflow from said common node to said output port at the end of each of oneor more cycles including a respective ith cycle of said first PWMwaveform, coupling said second PWM waveform to said lower controlterminal of said lower switching stage during an (i+1)th cycle of saidfirst PWM waveform, thereby causing said buck mode DC-DC converter tooperate in synchronous buck mode for the (i+1)th cycle of said first PWMwaveform; and (b) in response to inductor current dropping to zeroduring said one or more cycles including said respective ith cycle ofsaid first PWM waveform, producing diode emulation of said lowerswitching stage during the (i+1)th cycle of said first PWM waveform,thereby causing said buck mode DC-DC converter to operate in standardbuck mode for the (i+1)th cycle of said first PWM waveform.
 9. Themethod according to claim 8, wherein step (a) comprises storinginformation representative of the direction of inductor current flow forsaid ith cycle of said first PWM waveform, and selectively causing saidbuck mode DC-DC converter to operate in synchronous buck mode for the(i+1)th cycle of said first PWM waveform, in response to saidinformation being representative of positive inductor current flow. 10.The method according to claim 8, wherein step (b) comprises storinginformation representative of the direction of inductor current flow forsaid one or more cycles including said ith cycle of said first PWMwaveform, and selectively causing said buck mode DC-DC converter tooperate in standard buck mode for the (i+1)th cycle of said first PWMwaveform, in response to said information being representative of zeroinductor current flow.
 11. The method according to claim 8, furthercomprising the step (c) of controllably disabling steps (a) and (b) fora prescribed period of time following the termination of said first PWMwaveform.
 12. The method according to claim 8, wherein, in response to apositive inductor current flow from said common node to said output portduring said one or more cycles including said respective ith cycle ofsaid first PWM waveform, step (a) comprises generating said second PWMwaveform as the complement of said first PWM waveform, for applicationto said lower control terminal of said lower switching stage during the(i+1)th cycle of said first PWM waveform, thereby causing said buck modeDC-DC converter to operate in synchronous buck mode for the (i+1)thcycle of said first PWM waveform.
 13. The method according to claim 8,wherein, in response to a zero inductor current during said one or morecycles including said respective ith cycle of said first PWM waveform,step (b) comprises preventing said second PWM waveform from beingapplied to said lower control terminal of said lower switching stageduring the (i+1)th cycle of said first PWM waveform, thereby causingsaid buck mode DC-DC converter to operate in standard buck mode for the(i+1)th cycle of said first PWM waveform.
 14. A controller for a buckmode DC-DC converter comprised of an upper switching stage and a lowerswitching stage having controlled current flow paths therethroughcoupled between an input voltage terminal adapted to receive an inputvoltage, and a reference voltage terminal adapted to receive a referencevoltage, a common node between said upper switching stage and said lowerswitching stage being coupled through an output inductor to an outputport for charging a battery, said upper switching stage having an uppercontrol terminal to which a first pulse width modulation (PWM) waveformis applied for controlling the conduction and non-conduction of saidupper switching stage, and wherein said lower switching stage has alower control terminal to which a second PWM waveform, referenced tosaid first PWM waveform, is selectively applied for controlling theconduction and non-conduction of said lower switching stage, saidcontroller comprising: a storage device which is operative to storeinformation representative of the direction of inductor current flow forone or more cycles including an ith cycle of said first PWM waveform;and a logic circuit coupled to storage device and said lower switchingstage and being operative to selectively cause said buck mode DC-DCconverter to operate in one of synchronous buck mode and standard buckmode for an (i+1)th cycle of said first PWM waveform, based upon saidinformation stored by said storage device.
 15. The controller accordingto claim 14, wherein said logic circuit is operative, in response to apositive inductor current flow from said common node to said output portat the end of said one or more cycles including said ith cycle of saidfirst PWM waveform, to allow said second PWM waveform to be applied tosaid lower control terminal of said lower switching stage during said(i+1)th cycle of said first PWM waveform, and thereby cause said buckmode DC-DC converter to operate in synchronous buck mode for the (i+1)thcycle of said first PWM waveform.
 16. The controller according to claim14, wherein said logic circuit is operative, in response to saidinductor current being reduced to zero during one or more cyclesincluding said ith cycle of said first PWM waveform, to cause diodeemulation of said lower switching stage during the (i+1)th cycle of saidfirst PWM waveform, and thereby cause said buck mode DC-DC converter tooperate in standard buck mode for the (i+1)th cycle of said first PWMwaveform.
 17. The controller according to claim 14, further comprising aphase detector having inputs thereof coupled across the current flowpath through said second switching stage, and an output coupled to saidlogic circuit, and wherein said memory device comprises a flip-flophaving an input coupled to said output of said phase detector, a clockinput coupled to receive said first PWM waveform, and an output coupledto said logic circuit, and wherein said logic circuit is coupled toreceive said first PWM waveform and having an output coupled to saidlower control terminal of said lower switching stage.
 18. The controlleraccording to claim 17, wherein said lower switching stage controllerfurther comprises a blanking circuit which is operative to controllablydisable said phase detector for a prescribed period of time followingthe termination of said first PWM waveform.
 19. The controller accordingto claim 14, wherein, in response to a positive inductor current flowfrom said common node to said output port at the end of said one or morecycles including said ith cycle of said first PWM waveform, said logiccircuit is operative to generate said second PWM waveform as thecomplement of said first PWM waveform, for application to said lowercontrol terminal of said lower switching stage during the (i+1)th cycleof said first PWM waveform, and thereby cause said buck mode DC-DCconverter to operate in synchronous buck mode for the (i+1)th cycle ofsaid first PWM waveform.
 20. The controller according to claim 14,wherein, in response to a zero inductor current during said one or morecycles including said ith cycle of said first PWM waveform, said logiccircuit is operative to prevent said second PWM waveform from beingapplied to said lower control terminal of said lower switching stageduring the (i+1)th cycle of said first PWM waveform, and thereby causesaid buck mode DC-DC converter to operate in standard buck mode for the(i+1)th cycle of said first PWM waveform.
 21. A buck mode DC-DCconverter comprising: an inductor coupled to a battery; a high sideswitch having a first parallel diode, the high side switch coupledbetween the inductor and an input voltage source; a low side switchhaving a second parallel diode, the low side switch coupled between theinductor and a reference voltage; wherein the high side switch and thelow side switch are operated by a pulse width modulation (PWM) controlcircuit to charge the battery from the input voltage source; and a logiccircuit that opens the low side switch for a whole switching cycle whilethe PWM control circuit continues to operate the high side switch if theinductor current reaches approximately zero during the precedingswitching cycle, irrespective of the inductor current during the wholeswitching cycle.
 22. The converter of claim 21, wherein opening the lowside switch for a whole switching cycle, irrespective of the inductorcurrent during the whole switching cycle, thereby operates the buck modeconverter in standard mode during the whole switching cycle.
 23. Theconverter of claim 21, whereby the high side and low side switches areimplemented by MOSFET transistors and the first and second paralleldiodes are implemented by the body diodes of the MOSFET transistors. 24.A buck mode DC-DC converter comprising: a high side switch having afirst parallel diode, the high side switch coupled between an inductorand an input voltage source; a low side switch having a second paralleldiode, the low side switch coupled between the inductor and a referencevoltage; wherein the high side switch and the low side switch areoperated by a pulse width modulation (PWM) control circuit; and a logiccircuit that opens the low side switch while the PWM control circuitcontinues to operate the high side switch for a switching cycle when asignal related to inductor current drops below a threshold during thepreceding switching cycle, irrespective of inductor current during theswitching cycle, and wherein the logic circuit enables the low sideswitch when the inductor current reaches an output current threshold,irrespective of the inductor current during the switching cycle.
 25. Aswitching stage controller, comprising: a comparator that outputs acontrol signal based on a signal related to an inductor current flow;wherein the control signal indicates a synchronous buck mode operationfor an (i+1)th cycle of a pulse width modulation (PWM) waveform when thesignal related to an inductor current flow is above a first thresholdduring an entire ith cycle of the PWM waveform, irrespective of theinductor current flow during the (i+1)th cycle; and wherein the controlsignal indicates a standard buck mode operation for the (i+1)th cycle ofthe PWM waveform when the signal related to an inductor current flowfalls below a second threshold during an ith cycle of the PWM waveform,irrespective of the inductor current flow during the (i+1)th cycle. 26.A controller for a voltage regulator, the controller comprising: a pulsewidth modulation (PWM) generation circuit that is configured to generatePWM signals to control upper and lower switches in the voltageregulator; a node adapted to receive a feedback signal related to aninductor current of the voltage regulator; and a comparator, coupled tothe node, that outputs a control signal based on the feedback signalrelated to the inductor current flow; wherein the control signalindicates a synchronous buck mode operation for an (i+1)th cycle of afirst PWM waveform of the PWM generation circuit when the signal relatedto an inductor current flow is above a first threshold during an entireith cycle of the first PWM waveform and irrespective of the inductorcurrent flow during the (i+1)th cycle; and wherein the control signalindicates a standard buck mode operation for the (i+1)th cycle of thefirst PWM waveform of the PWM generation circuit when the signal relatedto an inductor current flow falls below a second threshold during an ithcycle of the first PWM waveform and irrespective of the inductor currentflow during the (i+1)th cycle.
 27. The controller of claim 26, furthercomprising a blanking circuit which is operative to controllably disablea phase detector for a prescribed period of time following a transitionof the PWM waveform.
 28. The controller of claim 26, wherein, inresponse to the inductor current flow above the first threshold at theend of one or more cycles including the ith cycle of the first PWMwaveform and irrespective of the inductor current flow during the(i+1)th cycle, the PWM generation circuit generates a second PWMwaveform, wherein a portion of the second PWM waveform is substantiallycomplementary to a portion of the first PWM waveform.